TY  - GEN
T1  - Verification of systems and circuits using LOTOS, Petri Nets, and CCS
T2  - Wiley series on parallel and distributed computing.
A1  - Yoeli, Michael, 1917-
A2  - Kol, Rakefet.
LA  - English
PP  - Hoboken, N.J.
PB  - Wiley-Interscience
YR  - 2008
UL  - https://colectivo.uloyola.es/Record/ELB177497
OP  - 231
CN  - TK7874.58 .Y64 2008
KW  - Integrated circuits : Verification.
KW  - Computer software : Verification.
KW  - LOTOS (Computer program language)
KW  - Petri nets.
KW  - Electronic books.
ER  -